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ltc2654 1 2654f block diagram description quad 16-/12-bit rail-to-rail dacs with 10ppm/c max reference the ltc ? 2654 is a family of quad 16-/12-bit rail-to-rail dacs with integrated 10ppm/c maximum reference . the dacs have built-in high performance, rail-to-rail, output buffers and are guaranteed monotonic. the ltc2654-l has a full-scale output of 2.5v with the integrated refer- ence and operates from a single 2.7v to 5.5v supply. the ltc2654-h has a full-scale output of 4.096v with the integrated reference and operates from a 4.5v to 5.5v supply. each dac can also operate with an external reference, which sets the full-scale output to 2 times the external reference voltage. these dacs communicate via a spi/microwire compat- ible 4-wire serial interface which operates at clock rates up to 50mhz. the ltc2654 incorporates a power-on reset circuit that is controlled by the porsel pin. if porsel is tied to gnd the dacs reset to zero-scale. if porsel is tied to v cc , the dacs reset to mid-scale. features applications n precision reference 10ppm/c max n maximum inl error: 4lsb at 16-bits n low 2mv (max) offset error n guaranteed monotonic over temperature n selectable internal or external reference n 2.7v to 5.5v supply range (ltc2654-l) n integrated reference buffers n ultralow crosstalk between dacs (<3nv?s) n power-on-reset to zero-scale/mid-scale n asynchronous dac update pin n tiny 20-lead 4mm 4mm qfn and 16-lead narrow ssop packages n mobile communications n process control and industrial automation n instrumentation n automatic test equipment n automotive l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5396245, 6891433 and patent pending. inl curve code 128 inl (lsb) 42 31 0 C2 C1C3 C4 16384 49152 2654 ta01b 65535 32768 v cc = 5v 2654 ta01a gndv outa v outb sck cs /ld ldac reflo refin/out refcomp v cc v outd v outc porsel sdo sdi clr internal reference dac a control logic decode power-on reset dac b dac d dac c register 32-bit shift register register register register register register register register downloaded from: http:///
ltc2654 2 2654f absolute maximum ratings supply voltage (v cc ) ................................... C0.3v to 6v cs /ld, sck, sdi, ldac , clr , reflo .......... C0.3v to 6v v outa-d ............................C0.3v to min (v cc + 0.3v, 6v) refin/out, refcomp .....C0.3v to min (v cc + 0.3v, 6v) porsel, sdo ..................C0.3v to min (v cc + 0.3v, 6v) operating temperature range ltc2654c ................................................ 0c to 70c ltc2654i.............................................. C40c to 85c (notes 1, 2) gn package 16-lead plastic ssop narrow 12 3 4 5 6 7 8 top view 1615 14 13 12 11 10 9 reflo v outa refcomp v outb refin/out ldac cs /ld sck gndv cc v outd v outc porselclr sdo sdi t jmax = 150c, ja = 110c/w 20 19 18 17 16 6 7 8 top view 21 gnd uf package 20-lead (4mm s 4mm) plastic qfn 9 10 5 4 3 2 1 11 12 13 14 15 v outa refcomp v outb refin/out ldac dncv outd v outc porselclr reflognd v cc dncdnc cs /ld sck dnc sdi sdo t jmax = 150c, ja = 37c/w exposed pad (pin 21) is gnd, must be soldered to pcb pin configuration maximum junction temperature........................... 150c storage temperature range ................... C65c to 150c lead temperature (soldering gn-package, 10 sec) ....................... 300c downloaded from: http:///
ltc2654 3 2654f product selector guide ltc2654 b c uf Cl 16 #tr pbf lead free designator tape and reel tr = tape and reel resolution 16 = 16-bit 12 = 12-bit full-scale voltage, internal reference mode l = 2.5v h = 4.096v package type uf = 20-lead (4mm 4mm) plastic qfn gn = 16-lead narrow ssop temperature grade c = commercial temperature range (0c to 70c) i = industrial temperature range (C40c to 85c) electrical grade (optional) b = 4lsb inl (max) product part number consult ltc marketing for information on non-standard lead based ? nish parts. consult ltc marketing for parts speci? ed with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ downloaded from: http:///
ltc2654 4 2654f order information lead free finish tape and reel part marking* package description temperature range maximum inl ltc2654bcgn-l16#pbf ltc2654bcgn-l16#trpbf 654l16 16-lead narrow ssop 0c to 70c 4 ltc2654bign-l16#pbf ltc2654bign-l16#trpbf 654l16 16-lead narrow ssop C40c to 85c 4 ltc2654bcuf-l16#pbf ltc2654bcuf-l16#trpbf 54l16 20-lead (4mm 4mm) plastic qfn 0c to 70c 4 ltc2654biuf-l16#pbf ltc2654biuf-l16#trpbf 54l16 20-lead (4mm 4mm) plastic qfn C40c to 85c 4 ltc2654bcgn-h16#pbf ltc2654bcgn-h16#trpbf 654h16 16-lead narrow ssop 0c to 70c 4 ltc2654bign-h16#pbf ltc2654bign-h16#trpbf 654h16 16-lead narrow ssop C40c to 85c 4 ltc2654bcuf-h16#pbf ltc2654bcuf-h16#trpbf 54h16 20-lead (4mm 4mm) plastic qfn 0c to 70c 4 ltc2654biuf-h16#pbf ltc2654biuf-h16#trpbf 54h16 20-lead (4mm 4mm) plastic qfn C40c to 85c 4 ltc2654cgn-l12#pbf ltc2654cgn-l12#trpbf 654l12 16-lead narrow ssop 0c to 70c 1 ltc2654ign-l12#pbf ltc2654ign-l12#trpbf 654l12 16-lead narrow ssop C40c to 85c 1 ltc2654cuf-l12#pbf ltc2654cuf-l12#trpbf 54l12 20-lead (4mm 4mm) plastic qfn 0c to 70c 1 ltc2654iuf-l12#pbf ltc2654iuf-l12#trpbf 54l12 20-lead (4mm 4mm) plastic qfn C40c to 85c 1 ltc2654cgn-h12#pbf ltc2654cgn-h12#trpbf 654h12 16-lead narrow ssop 0c to 70c 1 ltc2654ign-h12#pbf ltc2654ign-h12#trpbf 654h12 16-lead narrow ssop C40c to 85c 1 ltc2654cuf-h12#pbf ltc2654cuf-h12#trpbf 54h12 20-lead (4mm 4mm) plastic qfn 0c to 70c 1 ltc2654iuf-h12#pbf ltc2654iuf-h12#trpbf 54h12 20-lead (4mm 4mm) plastic qfn C40c to 85c 1 consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ ltc2654b-l16/ltc2654-l12 (internal reference = 1.25v) symbol param eter conditions ltc2654-12 ltc2654b-16 units min typ max min typ max dc performance resolution l 12 16 bits monotonicity (note 3) l 12 16 bits dnl differential nonlinearity (note 3) l 0.1 0.5 0.3 1 lsb inl integral nonlinearity v cc = 5.5v, v ref = 2.5v (note 3) l 0.5 1 2 4 lsb load regulation v cc = 5v 10%, integral reference, mid-scale, C15ma i out 15ma l 0.04 0.125 0.6 2 lsb/ma v cc = 3v 10%, integral reference, mid-scale, C7.5ma i out 7.5ma l 0.06 0.25 1 4 lsb/ma zse zero-scale error l 13 13 m v v os offset error (note 4) l 1 2 1 2 mv v os temperature coef? cient 5 5 v/c ge gain error (note 13) l 0.02 0.1 0.02 0.1 %fsr gain temperature coef? cient 1 1 ppm/c electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise speci? ed. downloaded from: http:///
ltc2654 5 2654f electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise speci? ed. symbol parameter conditions min typ max units v out dac output span internal reference external reference = v extref 0 to 2.5 0 to 2 ? v extref vv psr power supply rejection v cc 10% C80 db r out dc output impedance v cc = 5v 10%, internal reference, mid-scale, C15ma i out 15ma v cc = 3v 10%, internal reference, mid-scale, C7.5ma i out 7.5ma ll 0.040.04 0.150.15 ? dc crosstalk due to full-scale output change (note 5) due to load current change (note 5)due to powering down (per channel) (note 5) 1.5 21 v v/ma v i sc short-circuit output current v cc = 5.5v v extref = 2.8v (note 6) code: zero-scale; forcing output to v cc (note 6) code: full-scale; forcing output to gnd (note 6) ll 2020 6565 mama v cc = 2.7v v extref = 1.4v code: zero-scale; forcing output to v cc code: full-scale; forcing output to gnd ll 1010 4545 mama ltc2654b-l16/ ltc2654-l12 (internal reference = 1.25v) symbol parameter conditions min typ max units reference reference output voltage 1.248 1.25 1.252 v reference temperature coef? cient (note 7) 2 10 ppm/c reference line regulation v cc 10% C80 db reference short-circuit current v cc = 5.5v, forcing output to gnd l 35 m a refcomp pin short-circuit current v cc = 5.5v, forcing output to gnd l 60 200 a reference load regulation v cc = 3v 10% or 5v 10%, i out = 100a sourcing 40 mv/ma reference output voltage noise density c refcomp = c refin/out = 0.1f, at f = 1khz 30 nv/ hz reference input range external reference mode (note 13) l 0.5 v cc /2 v reference input current l 0.001 1 a reference input capacitance (note 9) l 20 pf power supplyv cc positive supply voltage for speci? ed performance l 2.7 5.5 v i cc supply current v cc = 5v, internal reference on (note 8) v cc = 5v, internal reference off (note 8) v cc = 3v, internal reference on (note 8) v cc = 3v, internal reference off (note 8) ll l l 1.71.3 1.6 1.2 2.5 2 2.21.7 mama ma ma i sd supply current in shutdown mode v cc = 5v (note 8) l 3 a digital i/ov ih digital input high voltage v cc = 3.6v to 5.5v v cc = 2.7v to 3.6v ll 2.42.0 vv v il digital input low voltage v cc = 4.5v to 5.5v v cc = 2.7v to 4.5v ll 0.80.6 vv v oh digital output high voltage load current = C100a l v cc C 0.4 v v ol digital output low voltage load current = 100a l 0.4 v downloaded from: http:///
ltc2654 6 2654f electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise speci? ed. symbol parameter conditions min typ max units v out dac output span internal reference external reference = v extref 0 to 4.096 0 to 2? v extref vv psr power supply rejection v cc 10% C80 db r out dc output impedance v cc = 5v 10%, internal reference, mid-scale, C15ma i out 15ma l 0.04 0.15 ltc2654b-h16/ltc2654-h12 (internal reference = 2.048v) symbol param eter conditions ltc2654-12 ltc2654b-16 units min typ max min typ max dc performance resolution l 12 16 bits monotonicity (note 3) l 12 16 bits dnl differential nonlinearity (note 3) l 0.1 0.5 0.3 1 lsb inl integral nonlinearity (note 3) v cc = 5.5v, v ref = 2.5v l 0.5 1 2 4 lsb load regulation v cc = 5v 10%, integral reference, mid-scale, C15ma i out 15ma l 0.04 0.125 0.6 2 lsb/ma zse zero-scale error l 13 13 m v v os offset error (note 4) l 1 2 1 2 mv v os temperature coef? cient 5 5 v/c ge gain error (note 13) l 0.02 0.1 0.02 0.1 %fsr gain temperature coef? cient 1 1 ppm/c ltc2654b-l16/ ltc2654-l12 (internal reference = 1.25v) symbol parameter conditions min typ max units i lk digital input leakage v in = gnd to v cc l 1 a c in digital input capacitance (note 9) l 8p f ac performancet s settling time 0.024% (1lsb at 12 bits) (note 10) 0.0015% (1lsb at 16 bits) (note 10) 4.28.9 ss settling time for 1lsb step 0.024% (1lsb at 12 bits) 0.0015% (1lsb at 16 bits) 2.24.9 ss voltage output slew rate 1.8 v/s capacitive load driving 1000 pf glitch impulse at mid-scale transition (note 11) 3 nv ? s dac-to-dac crosstalk due to full-scale output change (note 12) 3 nv ? s multiplying bandwidth 150 khz e n output voltage noise density at f = 1khz at f = 10khz 8580 nv/ hz nv/ hz output voltage noise 0.1hz to 10hz, internal reference 0.1hz to 200khz, internal reference 8 400 v p-p v p-p the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise speci? ed. downloaded from: http:///
ltc2654 7 2654f electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise speci? ed. symbol parameter conditions min typ max units dc crosstalk due to full-scale output change (note 5) due to load current change (note 5)due to powering down (per channel) (note 5) 1.5 21 v v/ma v i sc short-circuit output current v cc = 5.5v v extref = 2.8v (note 6) code: zero-scale; forcing output to v cc (note 6) code: full-scale; forcing output to gnd (note 6) ll 2020 6565 mama ltc2654b-h16/ ltc2654-h12 (internal reference = 2.048v) symbol parameter conditions min typ max units reference reference output voltage 2.044 2.048 2.052 v reference temperature coef? cient (note 7) 2 10 ppm/c reference line regulation v cc 10% C80 db reference short-circuit current v cc = 5.5v, forcing output to gnd l 35 m a refcomp pin short-circuit current v cc = 5.5v, forcing output to gnd l 60 200 a reference load regulation v cc = 5v 10%, i out = 100a sourcing 40 mv/ma reference output voltage noise density c refcomp = c refin/out = 0.1f, at f = 1khz 35 nv/ hz reference input range external reference mode (note 13) l 0.5 v cc /2 v reference input current l 0.001 1 a reference input capacitance (note 9) l 20 pf power supplyv cc positive supply voltage for speci? ed performance l 4.5 5.5 v i cc supply current v cc = 5v, internal reference on (note 8) v cc = 5v, internal reference off (note 8) ll 1.91.5 2.5 2 mama i sd supply current in shutdown mode v cc = 5v (note 8) l 3 a digital i/ov ih digital input high voltage v cc = 4.5v to 5.6v l 2.4 v v il digital input low voltage v cc = 4.5v to 5.5v l 0.8 v v oh digital output high voltage load current = C100a l v cc C 0.4 v v ol digital output low voltage load current = 100a l 0.4 v i lk digital input leakage v in = gnd to v cc l 1 a c in digital input capacitance (note 9) l 8p f ac performancet s settling time 0.024% (1lsb at 12 bits) (note 10) 0.0015% (1lsb at 16 bits) (note 10) 4.67.9 ss settling time for 1lsb step 0.024% (1lsb at 12 bits) 0.0015% (1lsb at 16 bits) 2.03.8 ss voltage output slew rate 1.8 v/s capacitive load driving 1000 pf glitch impulse at mid-scale transition (note 11) 6 nv ? s dac-to-dac crosstalk due to full-scale output change (note 12) 3 nv ? s multiplying bandwidth 150 khz downloaded from: http:///
ltc2654 8 2654f electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise speci? ed. timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. ltc2654b-l16/ltc2654-l12/ltc2654b-h16/ltc2654-h12 symbol parameter conditions min typ max units v cc = 2.7v to 5.5v t 1 sdi valid to sck setup l 4n s t 2 sdi valid to sck hold l 4n s t 3 sck high time l 9n s t 4 sck low time l 9n s t 5 cs /ld pulse width l 10 ns t 6 lsb sck high to cs /ld high l 7n s t 7 cs /ld low to sck high l 7n s t 8 sdo propagation delay from sck falling edge c load = 10pf v cc = 4.5v to 5.5v v cc = 2.7v to 4.5v ll 2045 nsns t 9 clr pulse width l 20 ns t 10 cs /ld high to sck positive edge l 7n s t 12 ldac pulse width l 15 ns t 13 cs /ld high to ldac high or low transition l 200 ns sck frequency 50% duty cycle l 50 mhz note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltages with respect to gnd. note 3: linearity and monotonicity are de? ned from code k l to code 2 n C1, where n is the resolution and k l is the lower end code for which no output limiting occurs. for v ref = 2.5v and n = 16, k l = 128 and linearity is de? ned from code 128 to code 65535. for v ref = 2.5v and n = 12, k l = 8 and linearity is de? ned from code 8 to code 4,095. note 4: inferred from measurement at code 128 (ltc2654-16), or code 8 (ltc2654-12). note 5: dc crosstalk is measured with v cc = 5v and using internal reference, with the measured dac at mid-scale.note 6: this ic includes current limiting that is intended to protect the device during momentary overload conditions. junction temperature can exceed the rated maximum during current limiting. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 7: temperature coef? cient is calculated by dividing the maximum change in output voltage by the speci? ed temperature range. maximum temperature coef? cient is guaranteed for c-grade only. note 8: digital inputs at 0v or v cc . note 9: guaranteed by design and not production tested. note 10: internal reference mode. dac is stepped ? scale to ? scale and ? scale to ? scale. load is 2k in parallel with 200pf to gnd. note 11: v cc = 5v, internal reference mode. dac is stepped 1 lsb between half-scale and half-scale - 1. load is 2k in parallel with 200pf to gnd. note 12: dac to dac crosstalk is the glitch that appears at the output of one dac due to a full-scale change at the output of another dac. it is measured with v cc = 5v and using internal reference, with the measured dac at mid-scale. c refin/out = no load. note 13: gain error speci? cation may be degraded for reference input voltages less than 1v. see gain error vs reference input voltage curve in the typical performance characteristics section. ltc2654b-h16/ ltc2654-h12 (internal reference = 2.048v) symbol parameter conditions min typ max units e n output voltage noise density at f = 1khz at f = 10khz 8580 nv/ hz nv/ hz output voltage noise 0.1hz to 10hz, internal reference 0.1hz to 200khz, internal reference 12 450 v p-p v p-p downloaded from: http:///
ltc2654 9 2654f typical performance characteristics dnl vs temperature reference output voltage vs temperature sampling to 1lsb rising sampling to 1lsb falling integral nonlinearity (inl) differential nonlinearity (dnl) inl vs temperature ltc2654-l16 code 128 inl (lsb) 43 1 C1 20 C2C3 C4 16384 49152 2654 g01 65535 32768 v cc = 3v code 128 dnl (lsb) 1.00.5 0 C0.5C1.0 16384 49152 2654 g02 65535 32768 v cc = 3v temperature (c) C50 inl (lsb) 42 31 0 C2C3 C1C4 C30 110 90 2654 g03 130 C10 10 30 50 70 v cc = 3v inl (pos) inl (neg) temperature (c) C50 dnl (lsb) 1.00.5 0 C0.5C1.0 C30 110 90 2654 g04 130 C10 10 30 50 70 v cc = 3v dnl (pos) dnl (neg) temperature (c) C50 v ref (v) 1.2531.251 1.2521.250 1.249 1.248 1.247 C30 110 90 2654 g05 130 C10 10 30 50 70 v cc = 3v cs /ld 3v/div v out 200v/div 2654 g06 2s/div 8s 1/4 scale to 3/4 scale stepv cc = 3v, v fs = 2.50v r l = 2k, c l = 200pf cs /ld 3v/div v out 200v/div 2654 g07 2s/div 8.1s 3/4 scale to 1/4 scale stepv cc = 3v, v fs = 2.50v r l = 2k, c l = 200pf average of 2048 events downloaded from: http:///
ltc2654 10 2654f typical performance characteristics dnl vs temperature reference output voltage vs temperature settling to 1lsb rising settling to 1lsb falling integral nonlinearity (inl) differential nonlinearity (dnl) inl vs temperature ltc2654-h16 code 128 inl (lsb) 42 31 0 C2 C1C3 C4 16384 49152 2654 g08 65535 32768 v cc = 5v code 128 dnl (lsb) 1.00.5 0 C0.5C1.0 16384 49152 2654 g09 65535 32768 v cc = 5v temperature (c) C50 inl (lsb) 42 31 0 C2C3 C1C4 C30 110 90 2654 g10 130 C10 10 30 50 70 v cc = 5v inl (pos) inl (neg) temperature (c) C50 dnl (lsb) 1.00.5 0 C0.5C1.0 C30 110 90 2654 g11 130 C10 10 30 50 70 v cc = 5v dnl (pos) dnl (neg) temperature (c) C50 v ref (v) 2.0542.052 2.050 2.048 2.046 2.044 2.042 C30 110 90 2654 g12 130 C10 10 30 50 70 v cc = 5v cs /ld 5v/div v out 250v/div 2654 g13 2s/div 7.9s 1/4 scale to 3/4 scale stepv cc = 5v, v fs = 4.096v r l = 2k, c l = 200pf average of 2048 events cs /ld 5v/div v out 250v/div 2654 g14 2s/div 6.8s 3/4 scale to 1/4 scale stepv cc = 5v, v fs = 4.096v r l = 2k, c l = 200pf average of 2048 events downloaded from: http:///
ltc2654 11 2654f typical performance characteristics load regulation current limiting headroom at rails vs output current offset error vs temperature zero-scale error vs temperature gain error vs temperature integral nonlinearity (inl) differential nonlinearity (dnl) settling to 1lsb (12-bit) rising ltc2654-12 ltc2654-16 code 0 inl (lsb) 1.00.5 0 C0.5C1.0 1024 3072 2654 g15 4095 2048 v cc = 5v v ref = 2.048v code 0 dnl (lsb) 1.00.5 0 C0.5C1.0 1024 3072 2654 g16 4095 2048 v cc = 3v v ref = 1.25v cs /ld 5v/div v out 1mv/div 2654 g17 2s/div 4.6s 1/4 scale to 3/4 scale stepv cc = 5v, v fs = 4.095v, r l = 2k, c l = 200pf average of 2048 events i out (ma) internal refcode = mid-scale C50 $ v out (v) 10 4 6 82 0 C4 C2C6 C8 C10 C30 C40 40 30 2654 g18 50 C20 C10 0 10 20 v cc = 5v (ltc2654-h) v cc = 3v (ltc2654-l) i out (ma) internal refcode = mid-scale C50 $ v out (v) 0.200.05 0.10 0.15 0 C0.05C0.10 C0.15 C0.20 C30 C40 40 30 2654 g19 50 C20 C10 0 10 20 v cc = 5v (ltc2654-h) v cc = 3v (ltc2654-l) i out (ma) 0 v out (v) 5.03.5 4.0 4.53.0 2.5 2.0 1.0 0.5 1.5 0 2 19 8 2654 g20 10 34567 5v (ltc2654-h) sourcing 3v (ltc2654-l) sourcing 5v (ltc2654-h) sinking 3v (ltc2654-h) sinking temperature (c) C50 offset error (mv) 31 20 C1C2 C3 C10 C30 110 2654 g21 130 10 30 50 70 90 temperature (c) C50 zero-scale error (mv) 3.02.0 2.51.5 1.0 0.5 0 C10 C30 110 2654 g22 130 10 30 50 70 90 temperature (c) C50 gain error (lsb) 6432 16 48 0 C32 C16C48 C64 C10 C30 110 2654 g23 130 10 30 50 70 90 downloaded from: http:///
ltc2654 12 2654f typical performance characteristics supply current vs logic voltage hardware clr to mid-scale hardware clr multiplying bandwidth large-signal response mid-scale glitch impulse offset error vs reference input gain error vs reference input i cc shutdown vs v cc ltc2654-16 reference voltage (v) 0.5 offset error (mv) 2.01.0 0.5 1.5 0 C1.0 C0.5C1.5 C2.0 1 2654 g24 2.5 1.5 2 v cc = 5.5v offset error of 4 channels reference voltage (v) 0.5 gain error (lsb) 6432 16 48 0 C32 C16C48 C64 1 2654 g25 2.5 1.5 2 v cc = 5.5v offset error of 4 channels v cc (v) 2.5 i cc (na) 450300 350250 400200 100 150 50 0 3 3.5 4 2654 g26 5.5 4.5 5 logic voltage (v) 0 i cc (na) 3.52.3 2.71.9 3.11.5 12 2654 g27 5 34 sweep sck, sdi, cs /ld between 0v and v cc v cc = 5v (ltc2654-h) v cc = 3v (ltc2654-l) clr 3v/div v out 1v/div 2654 g28 1s/div v cc = 3v, v ref = 1.25v code = full-scale clr 3v/div v out 1v/div 2654 g29 1s/div v cc = 3v, v ref = 1.25v code = full-scale frequency (hz) 1k bandwidth (db) 82 40 6 C2C6 C4C8 C10C12 10k 2654 g30 1m 100k v cc = 5v v ref(dc) = 2v v ref(ac) = 0.2v p-p code = full-scale v out 1v/div 2654 g31 2.5s/div ltc2654-h16 v cc = 5v, v fs = 4.095v zero-scale to full-scale v out 5mv/div v out 5mv/div cs /ld 5mv/div 2654 g32 2s/div ms ms-1 ltc2654-h16 v cc = 5v, 5nv-s typ ltc2654-l16 v cc = 3v, 3nv-s typ downloaded from: http:///
ltc2654 13 2654f typical performance characteristics ltc2654-16 power-on reset to mid-scale noise voltage vs frequency dac output 0.1hz to 10hz voltage noise reference 0.1hz to 10hz voltage noise dac to dac crosstalk (dynamic) power-on reset glitch v out 2mv/div v out 2mv/div one dac switch 0-fs 2v/div 2654 g33 2s/div ltc2654-l16, v cc = 5v, 4nv typ c refcomp = 1000pf c refout = no load ltc2654-l16, v cc = 5v c refcomp = c refout = 0.22f v cc 2v/div v out 10mv/div 2654 g34 200s/div zero-scale v cc 2v/div v out 1v/div 2654 g35 1ms/div ltc2654-l frequency (hz) 10 noise voltage (nv/ hz ) 400100 200 300 0 10k 1k 100 2654 g36 1m 100k v cc = 5v code = mid-scaleinternal ref c refcomp = c refout = 0.1f ltc2654-h ltc2654-l 5v/div 2654 g37 1s/div v cc = 5v, ltc2654-h code = mid-scaleinternal ref c refcomp = c refout = 0.1f 2v/div 2654 g38 1s/div v refout = 2.048v c refcomp = c refout = 0.1f downloaded from: http:///
ltc2654 14 2654f pin functions v outa to v outd (pins 1, 3, 13, 14/pins 2,4,13,14): dac analog voltage outputs. the output range is 0v to 2 times the voltage at the refin/out pin. refcomp (pin 2/pin 3): internal reference compensa- tion pin. for low noise and reference stability, tie a 0.1f capacitor to gnd. connecting this pin to gnd allows the use of external reference at start-up. refin/out (pin 4/pin 5): reference input/output. this pin acts as the internal reference output in internal refer- ence mode and acts as the reference input pin in external reference mode. when acting as an output the nominal voltage at this pin is 1.25v for -l options and 2.048v for -h options. for low noise and reference stability tie a capacitor to gnd. capacitor value must be c refcomp . in external reference mode, the allowable reference input voltage range is 0.5v to v cc /2. ldac (pin 5/pin 6): asynchronous dac update pin. if cs /ld is high, a falling edge on ldac immediately updates the dac register with the contents of the input register (similar to a software update). if cs /ld is low when ldac goes low, the dac register is updated after cs /ld returns high. a low on the ldac pin powers up the dac outputs. all the software power-down commands are ignored if ldac is low when cs /ld goes high. cs /ld (pin 6/pin 7): serial interface chip select/load input. when cs /ld is low, sck is enabled for shifting data on sdi into the register. when cs /ld is taken high, sck is disabled and the speci? ed command (see table 1) is executed. sck (pin 7/pin 8): serial interface clock input. cmos and ttl compatible. dnc (pins 8, 15, 16, 17/na): do not connect these pins. sdi (pin 9/pin 9): serial interface data input. data is ap- plied to sdi for transfer to the device at the rising edge of sck (pin 10). the ltc2654 accepts input word lengths of either 24 or 32 bits. see figures 2a and 2b. sdo (pin 10/pin 10): serial interface data output. this pin is used for daisy-chain operation. the serial output of the shift register appears at the sdo pin. the data transferred to the device via the sdi pin is delayed 32 sck rising edges before being output at the next falling edge. this pin is continuously driven and does not go high impedance when cs /ld is taken active high. clr (pin 11/pin 11): asynchronous clear input. a logic low at this level-triggered input clears all registers and causes the dac voltage outputs to drop to 0v if porsel pin is tied to gnd. if the porsel pin is tied to v cc , a logic low at clr sets all registers to mid-scale code and causes the dac voltage outputs to go to mid-scale.porsel (pin 12/pin 12): power-on-reset select pin. if tied to gnd, the dacs reset to zero-scale. if tied to v cc , the dacs reset to mid-scale. v cc (pin 18/pin 15): supply voltage input. for -l op- tions, 2.7v v cc 5.5v, and for -h options, 4.5v v cc 5.5v. should be bypassed by a 0.1f low esr ceramic capacitor to gnd. gnd (pin 19, exposed pad pin 21/pin 16): ground. exposed pad must be soldered to pcb ground.reflo (pin 20/pin 1): reference low pin. the voltage at this pin sets the zero-scale voltage of all dacs. this pin should be tied to gnd. (qfn/ssop) downloaded from: http:///
ltc2654 15 2654f block diagram timing diagrams figure 1a figure 1b sdi sdo cs /ld sck 2654 f01a t 2 t 10 t 5 t 7 t 6 t 1 ldac t 3 t 4 1232 32 4 t 13 t 12 t 8 cs /ld 2654 f01b t 13 ldac 2636 bd gndv outa v outb sck cs /ld ldac reflo refin/out refcomp v cc v outd v outc porsel sdo sdi clr internal reference dac a control logic decode power-on reset dac b dac d dac c register 32-bit shift register register register register register register register register downloaded from: http:///
ltc2654 16 2654f operation the ltc2654 is a family of quad voltage output dacs in 20-lead 4mm 4mm qfn and in 16-lead narrow ssop packages. each dac can operate rail-to-rail in external reference mode, or with its full-scale voltage set by an integrated reference. four combinations of accuracy (16- bit and 12-bit), and full-scale voltage (2.5v or 4.096v) are available. the ltc2654 is controlled using a 4-wire spi/microwire compatible interface. power-on reset the ltc2654-l/ltc2654-h clear the output to zero-scale if porsel pin is tied to gnd, when power is ? rst applied, making system initialization consistent and repeatable. for some applications, downstream circuits are active during dac power-up, and may be sensitive to nonzero outputs from the dac during this time. the ltc2654 con- tains circuitry to reduce the power-on glitch. the analog outputs typically rise less than 10mv above zero-scale during power-on if the power supply is ramped to 5v in 1ms or more. in general, the glitch amplitude decreases as the power supply ramp time is increased. see power- on-reset glitch in the typical performance characteristics section. alternatively, if porsel pin is tied to v cc (pin 18/pin 15), the ltc2654-l/ltc2654-h set the output to mid-scale when power is ? rst applied. power supply sequencing and start-up for ltc2654 family of parts, the internal reference is powered-up at start-up by default. if an external reference is to be used, the refcomp pin (pin 2/pin 3) must be hardwired to gnd. having refcomp hardwired to gnd at power up, will cause the refin/out pin to become high-impedance and will allow for the use of an external reference at start-up. however in this con? guration, internal reference will still be on, even though it is disconnected from the refin/out pin and it will draw supply current. in order to use external reference after power-up, the com- mand select external reference (0111b) should be used to turn the internal reference off (see table 1). the voltage at refin/out (pin 4/pin 5) should be kept within the range C0.3v refin/out v cc + 0.3v (see absolute maximum ratings). particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at v cc (pin 18/ pin 15) is in transition. transfer function the digital-to-analog transfer function is v out(ideal) = k 2 n ?? ? ?? ? ?2? v ref ? v reflo ?? ?? + v reflo where k is the decimal equivalent of the binary dac input code, n is the resolution of the dac, and v ref is the volt- age at the refin/out pin. the resulting dac output span is 0v to 2? v ref , as it is necessary to tie reflo to gnd. v ref is nominally 1.25v for ltc2654-l and 2.048v for ltc2654-h, in internal reference mode. table 1. command and address codes command* c3 c2 c1 c0 0 0 0 0 write to input register n 0 0 0 1 update (power-up) dac register n 0 0 1 0 write to input register n , update (power-up) all 0 0 1 1 write to and update (power-up) n 0 1 0 0 power-down n 0 1 0 1 power-down chip (all dacs and reference) 0 1 1 0 select internal reference (power-up reference) 0 1 1 1 select external reference (power-down reference) 1 1 1 1 no operation address ( n )* a3 a2 a1 a0 0 0 0 0 dac a 0 0 0 1 dac b 0 0 1 0 dac c 0 0 1 1 dac d 1 1 1 1 all dacs *command and address codes not shown are reserved and should not be used. downloaded from: http:///
ltc2654 17 2654f operation serial interfacethe cs /ld input is level triggered. when this input is taken low, it acts as a chip-select signal, powering on the sdi and sck buffers and enabling the input shift register. data (sdi input) is transferred at the next 24 rising sck edges. the 4-bit command, c3-c0, is loaded ? rst; followed by the 4-bit dac address, a3-a0; and ? nally the 16-bit data word. for the ltc2654-16 the data word comprises the 16-bit input code, ordered msb-to-lsb. for the ltc2654- 12 the data word comprises the 12-bit input code, ordered msb-to-lsb followed by four dont-care bits. data can only be transferred to the ltc2654 when the cs /ld signal is low. the rising edge of cs /ld ends the data transfer and causes the device to carry out the action speci? ed in the 24-bit input word. the complete sequence is shown in figure 2a. the command (c3-c0) and address (a3-a0) assignments are shown in table 1. the ? rst four commands in the table consist of write and update operations. a write operation loads a 16-bit data word from the 32-bit shift register into the input register of the selected dac, n . an update operation copies the data word from the input register to the dac register. once copied into the dac register, the data word becomes the active 16- or 12-bit input code, and is converted to an analog voltage at the dac output. the update operation also powers up the selected dac if it had been in power-down mode. the data path and registers are shown in the block diagram. while the minimum input word is 24 bits, it may option- ally be extended to 32 bits. to use the 32-bit word width, 8 dont-care bits are transferred to the device ? rst, followed by the 24-bit word as just described. figure 2b shows the 32-bit sequence. the 32-bit word is required for daisy chain operation, and is also available to accommodate microprocessors that have a minimum word width of 16 bits (2 bytes). the 16-bit data word is ignored for all commands that do not include a write operation. daisy-chain operationthe serial output of the shift register appears at the sdo pin. data transferred to the device from the sdi input is delayed 32 sck rising edges before being output at the next sck falling edge. the sdo pin is continuously driven and does not go high impedance when cs /ld is taken active high. the sdo output can be used to facilitate control of multiple serial devices from a single 3-wire serial port (i.e., sck, sdi and cs /ld). such a daisy-chain series is con? gured by connecting sdo of each up-stream device to sdi of the next device in the chain. the shift registers of the devices are thus connected in series, effectively forming a single input shift register which extends through the entire chain. because of this, the devices can be addressed and con- trolled individually by simply concatenating their input words; the ? rst instruction addresses the last device in the chain and so forth. the sck and cs /ld signals are common to all devices in the series. in use, cs /ld is ? rst taken low. then the concatenated input data is transferred to the chain, using sdi of the ? rst device as the data input. when the data transfer is complete, cs /ld is taken high, completing the instruction sequence for all devices simultaneously. a single device can be controlled by using the no-operation command (1111b) for the other devices in the chain. power-down mode for power-constrained applications, power-down mode can be used to reduce the supply current whenever less than four dac outputs are needed. when in power-down, the buffer ampli? ers, bias circuits and integrated reference circuits are disabled, and draw essentially zero current. the dac outputs are put into a high-impedance state, and the output pins are passively pulled to ground through individual 80k resistors. input- and dac-register contents are not disturbed during power-down. downloaded from: http:///
ltc2654 18 2654f operation figure 2a. ltc2654-16 24-bit load sequence (minimum input word) ltc2654-12 sdi data word: 12-bit input code + 4 dont care bits figure 2b. ltc2654-16 32-bit load sequence. ltc2654-12 sdi/sdo data word: 12-bit input code + 4 dont care bits 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 cs /ld sck sdi command word address data word 24-bit input word 2654 f02a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 x x x x x x x x cs /ld sck sdi c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 x x x x x x x x sdo command word data word dont care address word 2654 f02b previous 32-bit input word current 32-bit input word t 2 t 1 t 3 t 4 t 8 previous d15 previous d14 d15 18 17 sdi sdo sck d14 downloaded from: http:///
ltc2654 19 2654f operation any channel or combination of dac channels can be put into power-down mode by using command 0100b in combination with the appropriate dac address, ( n ). the integrated reference is automatically powered down when external reference is selected using command 0111b. in addition, all the dac channels and the integrated refer- ence together can be put into power-down mode using power-down chip command 0101b. for all power-down commands the 16-bit data word is ignored, but still needs to be clocked in. normal operation resumes by executing any command which includes a dac update, in software as shown in table 1 or by taking the asynchronous ldac pin low. the selected dac is powered up as its voltage output is updated. when a dac which is in a powered-down state is powered up and updated, normal settling is delayed. if less than four dacs are in a powered-down state prior to the update command, the power-up delay time is 12s. if on the other hand, all four dacs and the integrated reference are powered down, then the main bias generation circuit block has been automatically shut down in addition to the individual dac ampli? ers and integrated reference. in this case, the power up delay time is 14s. the power-up of integrated reference depends on the command that pow- ered it down. if the reference is powered down using the select external reference command (0111b) then it can only be powered back-up using select internal reference command (0110b). however if the reference was powered down using power-down chip command (0101b) then in addition to select internal reference command (0110b), any command that powers up the dacs will also power-up the integrated reference. asynchronous dac update using ldac in addition to the update commands shown in table 1, the ldac pin asynchronously updates all the dac registers with the contents of the input registers.if cs /ld is high, a low on the ldac pin causes all the dac registers to be updated with the contents of the in-put registers. if cs /ld is low, a low going pulse on the ldac pin before the rising edge of cs /ld powers up all the dac outputs but does not cause the output to be updated. if ldac remains low after the rising edge of cs /ld, then ldac is recognized, the command speci? ed in the 24-bit word just transferred is executed and the dac outputs are updated. the dac outputs are powered up when ldac is taken low, independent of the state of cs /ld. the integrated reference is also powered up if it was powered down us- ing power-down chip (0101b) command. the integrated reference will not power up when ldac is taken low, if it was powered down using select external reference (0111b) command. if ldac is low at the time cs /ld goes high, it inhibits any software power-down command (power-down n , power- down chip, select external reference) that was speci? ed in the input word.reference modes for applications where an accurate external reference is not available, the ltc2654 has a user-selectable, inte- grated reference. the ltc2654-l has a 1.25v reference that provides a full-scale output of 2.5v. the ltc2654-h has a 2.048v reference that provides a full-scale output of 4.096v. both references exhibit a typical temperature drift of 2ppm/c. internal reference mode can be selected by using command 0110b, and is the power-on default. a buffer is needed if the internal reference is required to drive external circuitry. for reference stability and low noise, connect a 0.1f capacitor between refcomp and gnd. in this con? guration, the internal reference can drive up to 0.1f capacitive load without any stability problems. in order to ensure stable operation, the capacitive load on refin/out pin should not exceed the capacitive load on the refcomp pin. the dac can also operate in external reference mode using command 0111b. in this mode, refin/out pin acts as an input that sets the dacs reference voltage. the input is high impedance and does not load the external reference source. the acceptable voltage range at this pin is 0.5v refin/out v cc /2. the resulting full-scale output voltage is 2? v refin/out . for using external reference at start-up, see the power supply sequencing and start-up section. downloaded from: http:///
ltc2654 20 2654f operation integrated reference buffers each of the four dacs in the ltc2654 has its own inte- grated high performance reference buffer. the buffers have very high input impedance and do not load the reference voltage source. these buffers shield the reference voltage from glitches caused by dac switching and thus minimize dac-to-dac dynamic crosstalk. typically dac-to-dac crosstalk is less than 3nv? s. by tying 0.22f capacitors between refcomp and gnd, and also between refin/ out and gnd, this number can be reduced to less than 1nv ? s. see the curve dac-to-dac dynamic crosstalk in the typical performance characteristics section. voltage outputs each of the ltc2654s four rail-to-rail output ampli? ers con- tained in these parts has guaranteed load regulation when sourcing or sinking up to 15ma at 5v (7.5ma at 3v). load regulation is a measure of the ampli? ers ability to maintain the rated voltage accuracy over a wide range of load conditions. the measured change in output voltage per milliampere of forced load current change is expressed in lsb/ma. dc output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from lsb/ma to ohms. the ampli? ers dc output impedance is 0.04 when driving a load well away from the rails. when drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 30 typical channel resistance of the output devices; e.g., when sinking 1ma, the minimum output voltage = 30 ? 1ma = 30mv. see the graph headroom at rails vs output current in the typical performance characteristics section. the ampli? ers are stable driving capacitive loads of up to 1000pf. board layout the excellent load regulation and dc crosstalk performance of these devices is achieved in part by keeping signal and power grounds separate. the pc board should have separate areas for the analog and digital sections of the circuit. this keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the devices ground pin as possible. ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. the gnd pin functions as a return path for power supply currents in the device and should be connected to analog ground. the reflo pin should be connected to system star ground. resistance from the reflo pin to system star ground should be as low as possible. rail-to-rail output considerations in any rail-to-rail voltage output device, the output is limited to voltages within the supply range. since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in figure 3b. similarly, limiting can occur in external refer- ence mode near full-scale when the refin/out pin is at v cc /2. if v refin/out = v cc /2 and the dac full-scale error (fse) is positive, the output for the highest codes limits at v cc as shown in figure 3c. no full-scale limiting can occur if v refin/out (v cc C fse)/2. offset and linearity are de? ned and tested over the region of the dac transfer function where no output limiting can occur. downloaded from: http:///
ltc2654 21 2654f operation figure 3. effects of rail-to-rail operation on a dac transfer curve. (a) overall transfer function (b) effect of negative offset for codes near zero scale (c) effect of positive full-scale error for codes near full-scale 2654 f04 input code (b) output voltage negative offset 0v 0v 32,768 0 4,095 input code output voltage (a) v ref = v cc v ref = v cc (c) input code output voltage positivefse downloaded from: http:///
ltc2654 22 2654f package description gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 ? .244 (5.817 ? 6.198) .150 ? .157** (3.810 ? 3.988) 16 15 14 13 .189 ? .196* (4.801 ? 4.978) 12 11 10 9 .016 ? .050 (0.406 ? 1.270) .015 .004 (0.38 0.10) 45 0 ? 8 typ .007 ? .0098 (0.178 ? 0.249) .0532 ? .0688 (1.35 ? 1.75) .008 ? .012 (0.203 ? 0.305) typ .004 ? .0098 (0.102 ? 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ? .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note:1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale downloaded from: http:///
ltc2654 23 2654f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description uf package 20-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1710) 4.00 0.10 4.00 0.10 note:1. drawing is proposed to be made a jedec package outline mo-220 variation (wggd-1)?to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1top mark (note 6) 0.40 0.10 20 19 12 bottom view?exposed pad 2.00 ref 2.45 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uf20) qfn 01-07 rev a recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.00 ref 2.45 0.05 3.10 0.05 4.50 0.05 package outline pin 1 notchr = 0.20 typ or 0.35 45 chamfer 2.45 0.10 2.45 0.05 downloaded from: http:///
ltc2654 24 2654f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0310 printed in usa typical application related parts part number description comments ltc1660/ltc1665 octal 10-/8-bit v out dacs in 16-pin narrow ssop v cc = 2.7v to 5.5v, micropower, rail-to-rail output ltc1664 quad 10-bit v out dac in 16-pin narrow ssop v cc = 2.7v to 5.5v, micropower, rail-to-rail output ltc1821 single 16-bit v out dac with 1lsb inl, dnl parallel interface, precision 16-bit settling in 2s for 10v step ltc2656 octal 16-/12-bit v out dacs 325a per dac, 2.7v to 5.5v supply range, rail-to-rail output, spi serial interface, internal reference ltc2601/ltc2611/ ltc2621 single 16-/14-/12-bit v out dacs in 10-lead dfn 300a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2602/ltc2612/ ltc2622 dual 16-/14-/12-bit v out dacs in 8-lead msop 300a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2604/ltc2614/ ltc2624 quad 16-/14-/12-bit v out dacs in 16-lead ssop 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2605/ltc2615/ ltc2625 octal 16-/14-/12-bit v out dacs with i 2 c interface 250a per dac, 2.7v to 5.5v supply range, rail-to-rail output ltc2606/ltc2616/ ltc2626 single 16-/14-/12-bit v out dacs with i 2 c interface 270a per dac, 2.7v to 5.5v supply range, rail-to-rail output ltc2609/ltc2619/ ltc2629 quad 16-/14-/12-bit v out dacs with i 2 c interface 250a per dac, 2.7v to 5.5v supply range, rail-to-rail output with separate v ref pins for each dac ltc2634 quad 12-/10-/8-bit v out dacs with 10ppm/c (typical) reference 125a per dac, 2.7v to 5.5v supply range, internal 1.25v or 2.048v reference, rail-to-rail output, spi interface ltc2636 octal 12-/10-/8-bit v out dacs with 10ppm/c reference 125a per dac, 2.7v to 5.5v supply range, internal 1.25v or 2.048v reference, rail-to-rail output, spi interface ltc2641/ltc2642 single 16-/14-/12-bit v out dacs with 1lsb inl, dnl 1lsb (max) inl, dnl, 3mm 3mm dfn and msop packages, 120a supply current, spi interface ltc2704 quad 16-/14-/12-bit v out dacs with 2lsb inl, 1lsb dnl software programmable output ranges up to 10v, spi interface ltc2754 quad 16-/14-/12-bit spi i out dacs with 1lsb inl, 1lsb dnl software programmable output ranges up to 10v spi interface ltc2755 quad 16-/14-/12-bit i out dacs with 1lsb inl, 1lsb dnl software programmable output ranges up to 10v, parallel interface true rail-to-rail output dac 2654 ta02 ltc2654 v cc refcomp refin/out ldac porsel clr gnd gnd dnc c1 0.1f dnc dnc dnc reflo cs /ld scksdi sdo v outa v outb v outc v outd c2 0.1f c3 0.1f d1bas70 18 19 21 8 17 16 15 20 pin numbers shown are for the qfn package. pins 5, 6, 7, 9, 11 tie to digital control lines 2451 2 1 1 r210k C5v 5v 13 13 14 67 9 10 downloaded from: http:///

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